Lehrstuhl für Schaltungsentwurf
Technische Universität München (TUM) - Arcisstr. 21 - 80333 München

Before starting with your design lab:

Please read the " LTE Design Labs - Getting started " guide !!!

Guidelines for Preparation of Final Presentation and Report Submission

Material for Preparation of Final Presentation and Report Submission

Report
Thesis template (Latex)
Final Presentation
LTE template for presentations
Guideline for presentations

Cadence Design Framework

Reference Card / Manual
Cadence Schnelleinstieg (German) (Cadence 5.1)
Cadence Short Manual (German) (old Cadence version)
Tutorials
Short Cadence Tutorial (Inverter circuit)
Cadence AMS Designer
Cadence VHDL Interface
Cadence NC Verilog

Documentation - Mixed-Signal IC Design Lab

Cadence Introduction
Introduction to Cadence 6.1 with Inverter Design Example
Introduction to Cadence 6.1 with Inverter Design Example (zip version with image files)
Articles
ADC Architectures - Which ADC architecture is right for your application?
Measurement considerations (A/D converters)
INL/DNL Measurements for High-Speed ADC's
Histogram Testing to Determine DNL and INL Errors
Dynamic Testing of High-Speed ADCs, Part 1
Dynamic Testing of High-Speed ADCs, Part 2
Understanding FFT Windows
Scripts
Matlab Script for plotting Spectrum and SNR Calculation

Documentation - Design of Power Management Circuits Lab

Scripts
Matlab Script for plotting Spectrum and SNR Calculation

Documentation - Design of Analog Circuits Lab

Articles
CMOS Device Characterization
Scripts
Matlab Script for plotting Spectrum and SNR Calculation